In a wireless mobile communication and signal processing system, for a hardware circuit (or an integrated circuit), usually, a flow of processing signal data input to a hardware module has to be designed based on a given algorithm, to achieve real-time data processing. For a common hardware circuit design (a functional sub-module in the integrated circuit), a starting/enabling signal corresponding to the hardware module is generally used as a trigger signal, a counter with a proper bit width is designed to accumulate operating clocks after the module is started, and the clock count value obtained by accumulating is used as a hardware clock cycle of a certain data processing flow in the corresponding algorithm description currently processed by the hardware. Generally, the hardware processing cycle can be predetermined. By analyzing the algorithm processing flow and the correspondence between the algorithm processing flow and the hardware circuit design, the hardware clock cycle corresponding to each algorithm processing flow can be predetermined. When the accumulated count value of the operating hardware clock reaches the predetermined hardware clock cycle, the current hardware processing is stopped, that is, the data processing flow defined in the algorithm description is finished.
In time division synchronous code division multiple access (TD-SCDMA) mobile communication base band processing system, particularly in the mobile terminal processing system at the user side, the algorithm flow designed based on joint detection is complex, and it is somewhat difficult for the hardware to perform the function. For example, in an algorithm flow of estimating channel transmission coefficients of a plurality of cells, it is necessary to perform downlink reception of midamble code and transfrom the midamble code from time-domain to frequency-domain (Fast Fourier Transform process, FFT), to eliminate interferences from the received midamble code in the frequency domain and the signals of all receiving cells, and then to perform the corresponding dot division operation of 128 dots with the basic midamble code of the current processing cell configured by software; to transform the data to the time-domain form by inverse FFT; next, for the transmission path in the transfer function, a multi-cell based joint main-path justification and a noise reduction process are performed to obtain a valid transmission path meeting the performance requirement; and finally, the data needs to be transformed to the frequency-domain form by FFT to perform the corresponding dot multiplication operation of 128 dots with the basic midamble code of the current processing cell configured by software to finish the reconstruction of a signal. Moreover, the processes above need to be iterated for many times according to the definition of performance simulation.
At present, most hardware designs are designed to be triggered under a counting condition of a counter and to generate a control signal in real time as a control flow. However, in the occasion that processing the TD-SCDMA terminal base band chip which has more complex implementation of function design and has a high demand on the control of data processing flow, it is very difficult to design the hardware fully satisfying the entire algorithm flow and it is very difficult to control the entire function implementation by using the control flow.